Design of a computational nonvolatile RAM for a greedy energy-efficient VLSI processor

A computational nonvolatile RAM (C-NVRAM), where magneto-resistive random access memory with spin-transfer torque magnetic tunnel junctions (STT-MTJs) is used as an on-chip storage element, combined with bit-parallel arithmetic modules is proposed for a greedy energy-efficient VLSI processors in the wide range of consumer electronics and mobile applications such as internet-of-things. A judicious combination of bit-serial/word-parallel (at a C-NVRAM) and bit-parallel processing manners makes the calculation cycles reduced in parallel computing such as an image processing. Moreover, since data-access rate of the MTJ-based nonvolatile memory is negligible (is only 1/104 percent of memory cell array), its power dissipation is dominated by its static power dissipation. Therefore, the use of nonvolatile memory makes the total power reduced greatly. As a typical application, it is demonstrated in parallel image processing with 8-bit-intensity 256×256 pixels that the energy (computing-time-power-dissipation product) of the proposed hardware is less than 1/15 in comparison with that of the corresponding CMOS-only-based one under a 90nm-CMOS/100nm-MTJ process technologies.