Characterization of FPGA-master ARM communication delays in Cyclone V devices

FPGAs have evolved from hardware accelerators to very powerful System-on-Chip platforms, mainly thanks to the availability of increasingly powerful embedded processors. The efficient integration of embedded processors with the FPGA fabric requires fast exchange of information between both sides, not to compromise the performance improvement these architectures should provide. Therefore, detailed performance analyses of different FPGA-processor communication scenarios are needed for designers to be able to evaluate the suitability of current devices for a given application, and to take the most advantage of them in it. This paper presents, to the best of authors´ knowledge, the first reported characterization of FPGA-processor communications in Altera Cyclone V SoC devices. In this initial step towards a comprehensive study, the performance of communication mechanisms where the processor acts as master is analyzed.