Low latency solver for linear equation systems in floating point arithmetic

Some applications, especially real time simulation systems, require to compute a linear system´s solution in a very short amount of time. FPGA are well known to offer low latency computation and current chips are dense enough to implement hundreds of floating point operators. However, their many-stage pipelined architecture and the high cost of the divisors make the implementation of low latency applications a real challenge. We propose a division free algorithm founded on Gauss-Jordan algorithm, which takes advantage of the floating point format (any precision) and which exploits as much as possible the pipelined architecture of the operators. Results demonstrate that current FPGA can solve linear systems larger than hundred equations within ten microseconds in single or double precision arithmetic. This represents a two order of magnitude improvement over previous implementations.