Low power test pattern generator for BIST

In the last years designers mainly concentrate on low power consumption in mobile computing devices and cellular phones. In this article new solutions for reducing a switching activity of Built-In Self Test (BIST) environment for the scan-organized BIST architectures is presented. The key idea behind this technique is based on the designing a new structure of LFSR to generate more than one pseudo random bit per one clock pulse. Theoretical calculations were hardware verified in two digital systems design environment: WebPACK ISE by Xilinx and Quartus II by Altera. Power consumption measure tools were Xilinx XPower and Altera PowerPlay Power Analyzer Tool. The practical verification covers power consumption of the Test Patternd Generator (TPG) as well as the complete BIST. Achieved results are over a dozen percent better comparing to a similar works. The paper is organized as follows. In section 2, the power consumption issue and weighted switching activity modeling are investigated, section 3 presents new algorithm for bits generation, in section 4 new approach of TPG is presented, section 5 describes tool for VHDL code generation, in section 6 research methodology is presented. Section 7 contains hardware verification of new approaches. In part 8 are presented results measured for the whole BIST and section 9 is the summary.