A compact complex-valued MIMO detector and its FPGA implementation

This paper presents a compact and efficient hard output MIMO detection and its FPGA implementation. Our method is based on a complex-valued decomposition and a highly compact expansion, which needs least number of visited nodes and a half of tree depth than previously published K-best designs. We propose a fully pipelined architecture, combining with resource sharing to realize the detector. Furthermore, our complex-valued MIMO detector is implemented and validated on a Xilinx FPGA device for a 16-QAM modulation and 4×4 antenna configuration. The implementation results show that the proposed detector is hardware efficient and has a 395 Mbps throughput with about 0.2dB performance loss.