Tail biting convolutional code decoder co-processor for high throughput System-on-Chip

In this paper proposed tail biting convolutional code decoder co-processor architecture design for high throughput AMBA bus based System on Chip. Proposed TBCC decoder configured for LTE application and integrated on Leon3 SoC. To support low complexity, reverse trellis algorithm choose as TBCC decoding algorithm. DMA used in integration process to ensure the inter-frame decoding process is continuous and uninterrupted. The coprocessor designs have been tested on a Altera Stratix IV, achieving a throughput of 221 Mbps.