• DocumentCode
    3742672
  • Title

    Global clock distribution using standing wave resonant on transmission lines

  • Author

    Jing Yang;Yong-bin Kim

  • Author_Institution
    Dept. of Electrical and Computer Engineering, Northeastern University, Boston, USA
  • fYear
    2015
  • Firstpage
    249
  • Lastpage
    250
  • Abstract
    In this paper, an X-tree clock distribution typology has been applied, a two stage, 7.5 mm * 7.5 mm dimension standing wave resonant clock distribution network can perfectly convey clock signals everywhere on to the chip without taking up much of the chip area (around 1.28mm2, which is 2.2% of the total chip area), and dissipating 51.75 mW power. The clock jitter is 1.86ps and almost zero clock skew.
  • Keywords
    "Clocks","Loading","Resistance","Jitter","Load modeling","Computational modeling","Simulation"
  • Publisher
    ieee
  • Conference_Titel
    SoC Design Conference (ISOCC), 2015 International
  • Type

    conf

  • DOI
    10.1109/ISOCC.2015.7401741
  • Filename
    7401741