Algorithm and Hardware Implementation for Generation of Low Power SIC Test Sequences

Single input change (SIC) test sequences have been investigated in recent years because it is effective to more test fault types and test power reduction. In this paper, generation of sequential SIC (SSIC) test sequences based on deterministic built-in self-test (BIST) is proposed for decreasing the test power consumption and test application time with high test fault coverage. Furthermore, several important properties of SSIC sequences are presented and discussed as the basic of seed selection. Proper selection of SIC seeds is the key technique to a successful deterministic BIST. The seeds of SSIC are generated using the properties of SSIC. A hardware structure is designed to generate SSIC sequences. Experimental results based on ISCAS´85 Benchmark circuits demonstrate that the proposed SSIC test sequences can reduce test power consumption and test application time than random SIC (RSIC) test sequences, and also keeping high test fault coverage.