Analysis of a serial link for power supply induced jitter

An analysis of power supply induced jitter in a high speed serial link is presented in this paper. An equivalent reduced model for serial link is used for the analysis. Jitter induced by the ripples in power delivery network is analyzed by a small signal equivalent model. The effect is modeled by a transfer function which is not technology specific and can be used generically for System-On-Chip (SoC) level design considerations. The analysis is supported by experimental results by simulation in 130nm BiCMoS RF technology and 28nm FDSOI technology (both technologies are of STMicroelectronics).