Reconfigurable hardware architecture of the spatial pooler for hierarchical temporal memory

Self-learning hardware systems, with high-degree of plasticity, are critical in performing spatio-temporal tasks in next-generation computing systems. To this end, hierarchical temporal memory (HTM) offers time-based online-learning algorithms that store and recall temporal and spatial patterns. One of the key building blocks in HTM is the spatial pooler. In this paper, we propose a reconfigurable and scalable spatial pooler architecture that is ported onto a Xilinx Virtex-IV FPGA fabric. The concept of synthetic synapses is proposed for dynamic interconnections. The spatial pooler architecture is verified for two different datasets, MNIST and EU numberplate font, with ≈ 91% and ≈ 90% accuracy respectively. Moreover, the proposed hardware model offers speed up of 4817X over the software realization. These results indicate that the proposed architecture can serve as a core to build the HTM in hardware and eventually as a standalone self-learning hardware system.