Design of time reduction for successive approximation register A/D converter

Acting as the gateway between the "real world" analog signal and digital signal, data converters have become a critical element of modern electronic devices. High-performance applications have put a particular emphasis on high-speed data conversion converters. A variety of converter architectures are being used to reach these higher speeds, each with special advantages. In modern life, the improvements of technologies and design methods have allowed to implement Successive Approximation Register (SAR) analog-to-digital converter (ADC) for higher performance. However, this converter has "N" time conversion steps required to digitize a sample for "N" bit due to the nature of successive approximation algorithm. To solve this situation, the new high performance architecture based on SAR ADC with charge redistribution DAC is created. In this paper, the proposed system modifies the SAR function to get high speed by reducing the number of bit cycles. Therefore, the proposed architecture can obtain better speed than the conventional architecture.