An on-chip delay measurement using adjacency testable scan design

This paper presents a Time to Digital Converter (TDC)-based low cost and high quality on-chip delay measurement with adjacency testable scan design. Adjacency test is useful for on-chip delay measurement with TDC because it can generate arbitrary 1-bit transition to arbitrary input with smaller number of seed vectors. However the area overhead is high because it requires an extra shift register whose length is the same as the number of registers to store seed vectors. The proposed adjacency testable scan design does not require the extra shift register for its Chiba scan-based architecture. Therefore the area overhead is lower. The evaluation shows that the number of sensitizable paths is 7.1 times of that of LOS-based measurement and it is 3.5 times of that of LOC-based measurement. The number of vectors is 56.2% of that of enhanced scan design on average. The area overhead is 49.3% on average, which is the same order of that of enhanced scan design-based measurement.