DocumentCode :
3748066
Title :
First demonstration of Ge nanowire CMOS circuits: Lowest SS of 64 mV/dec, highest gmax of 1057 ?S/?m in Ge nFETs and highest maximum voltage gain of 54 V/V in Ge CMOS inverters
Author :
Heng Wu;Wangran Wu;Mengwei Si;Peide D. Ye
Author_Institution :
School of Electrical and Computer Engineering, Purdue University, West Lafayette, IN 47906, U.S.A.
fYear :
2015
Abstract :
Ge nanowire CMOS circuits are experimentally demonstrated on a Ge on insulator (GeOI) substrate for the first time. The nanowire CMOS devices have channel lengths (Lch) from 100 to 40 nm, nanowire height (HNW) of 10 nm and nanowire widths (WNW) from 40 to 10 nm, and dielectric EOTs of 2 and 5 nm. Four types of Ge MOSFETs: accumulation mode (AM) and inversion mode (IM) nFETs and pFETs are studied in great details. Record low SS of 64 mV/dec and high maximum trans-conductance (gmax) of 1057 μS/μm are obtained on Ge nanowire nFETs. Furthermore, hybrid Ge nanowire CMOS with AM nFET and IM pFET is also first realized. The highest maximum voltage gain reaches 54 V/V.
Keywords :
"CMOS integrated circuits","Logic gates","Nanoscale devices","MOSFET","Three-dimensional displays","Inverters","Substrates"
Publisher :
ieee
Conference_Titel :
Electron Devices Meeting (IEDM), 2015 IEEE International
Electronic_ISBN :
2156-017X
Type :
conf
DOI :
10.1109/IEDM.2015.7409610
Filename :
7409610
Link To Document :
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