• DocumentCode
    3748152
  • Title

    ESD characterization of gate-all-around (GAA) Si nanowire devices

  • Author

    S.-H. Chen;D. Linten;G. Hellings;A. Veloso;M. Scholz;R. Boschke;G. Groeseneken;N. Collaert;A. Thean

  • Author_Institution
    imec, B-3001 Leuven, Belgium
  • fYear
    2015
  • Abstract
    In CMOS scaling roadmap, gate-all-around (GAA) nanowire (NW) is a promising candidate in sub-10nm nodes. However, newly introduced process options in GAA NW technologies can result in significant impacts on intrinsic ESD performance. In this work, ESD protection devices in GAA NW architecture are studied and the corresponding 3D TCAD simulations bring an in-depth understanding.
  • Keywords
    "Logic gates","Stress","Electrostatic discharges","Voltage measurement","Leakage currents","Silicon","Anodes"
  • Publisher
    ieee
  • Conference_Titel
    Electron Devices Meeting (IEDM), 2015 IEEE International
  • Electronic_ISBN
    2156-017X
  • Type

    conf

  • DOI
    10.1109/IEDM.2015.7409696
  • Filename
    7409696
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3748152