DocumentCode
3748166
Title
High-K gate dielectric depletion-mode and enhancement-mode GaN MOS-HEMTs for improved OFF-state leakage and DIBL for power electronics and RF applications
Author
H. W. Then;L. A. Chow;S. Dasgupta;S. Gardner;M. Radosavljevic;V. R. Rao;S. H. Sung;G. Yang;P. Fischer
Author_Institution
Intel Corporation, Components Research, Technology and Manufacturing Group, Hillsboro, OR 97124, USA
fYear
2015
Abstract
The characteristics of high-k gate dielectric depletion-mode and enhancement-mode GaN MOS-HEMTs is reviewed. High-k gate dielectric depletion-mode GaN MOS-HEMT with thin AlInN polarization layer of 2.5nm in the gate stack is shown to exhibit "negative" capacitance and steep SS<;40mV/dec [31], which may have implications for low-power electronics. Enhancement-mode operation is achieved by removing the AlInN polarization layer from the gate stack [31-36]. Excellent DIBL, low IOFF, low gate leakage, and low RON are achieved due to the scaled Toxe=23Å using high-k gate dielectric and N+ regrown InGaN source/drain [32]. The DIBL and IOFF-RON characteristics of the high-k enhancement-mode GaN MOS-HEMT [32] are the best reported for a GaN transistor. These characteristics make the high-k gate dielectric depletion-mode and enhancement-mode GaN MOS-HEMT attractive for power electronics and RF applications.
Keywords
"Gallium nitride","Logic gates","HEMTs","Radio frequency","Capacitance","High K dielectric materials"
Publisher
ieee
Conference_Titel
Electron Devices Meeting (IEDM), 2015 IEEE International
Electronic_ISBN
2156-017X
Type
conf
DOI
10.1109/IEDM.2015.7409710
Filename
7409710
Link To Document