Investigation of PCB layout parasitics in EMI filtering of I/O lines

Author

Ye, Xiaoning ; Liu, Geping ; Drewniak, James L.

Author_Institution

Dept. of Electr. & Comput. Eng., Missouri Univ., Rolla, MO, USA

Volume

1

fYear

2001

fDate

2001

Firstpage

501

Abstract

EMI filters are often utilized on I/O lines to reduce high-frequency noise from being conducted or coupled off the PCB and resulting in an EMI problem. However, layout parasitics are usually inevitable in practical circuit design, and the filtering performance may vary. In this study, the impact of the board layout on the filtering performance is investigated by |S₂₁| measurements of sample PCB boards with different filter layouts. The finite-difference time-domain method is applied to model the boards, support the experimental work, and can be used to provide a means for conducting "what-if" engineering studies

Keywords

electromagnetic compatibility; electromagnetic interference; filters; finite difference time-domain analysis; printed circuit layout; printed circuits; "what-if" engineering studies; |S₂₁| measurements; EMC; EMI; EMI filters; I/O lines EMI filtering; PCB layout parasitics; filtering performance; finite-difference time-domain method; high-frequency noise filtering; Capacitors; Electromagnetic interference; Ferrites; Filtering; Finite difference methods; Frequency; Low pass filters; Microstrip filters; Surface-mount technology; Time domain analysis;

fLanguage

English

Publisher

ieee

Conference_Titel

Electromagnetic Compatibility, 2001. EMC. 2001 IEEE International Symposium on

Conference_Location

Montreal, Que.

Print_ISBN

0-7803-6569-0

Type

conf

DOI

10.1109/ISEMC.2001.950692

Filename

950692