Title :
Study of conductor surface roughness impact on package insertion loss
Author :
H. Louis Lo;Bok Eng Cheah
Author_Institution :
Intel Corporation, 1900 Prairie City Rd. Folsom, CA 95630
Abstract :
This paper investigates and discusses the impact of surface roughness on package insertion loss performance for high-speed applications up-to 50GHz. 3D electrical package with Hurray surface roughness modeling was established and simulated. The insertion loss performance of package interconnects are discussed and compared against laboratory measurement results. The magnitude of electrical insertion loss due to surface roughness on the horizontal metal routing and vertical interconnects for instance plated through hole structure is also evaluated. Sensitivity of dielectric thickness in mitigating insertion loss performance degradation due to surface roughness is also presented in this paper.
Keywords :
"Rough surfaces","Surface roughness","Insertion loss","Dielectric losses","Transmission line measurements","Conductors"
Conference_Titel :
Electronics Packaging and Technology Conference (EPTC), 2015 IEEE 17th
DOI :
10.1109/EPTC.2015.7412292