A non-sequential phase detector for PLL-based high-speed data/clock recovery

The Phase-Locked Loop (PLL) is a widely used block in data and clock recovery circuits. Phase detectors form a crucial part of the PLL. The requirements for phase detectors used in random data recovery are more stringent than the one used for clock recovery, especially at high-speed. This paper presents a new Phase Detector (PD) that can be used for high-speed random data/clock recovery. In contrast to most existing structures which are speed-limited by sequential logic circuits, it exploits the leading and lagging signals from the VCO which greatly simplifies the PD structure. Using the HSPICE simulator and HP 0.35 u standard CMOS process models, simulation results show that the PD can operate at 2 GHz over the 0°C to 100°C temperature range and over fast and slow process corners