Efficient implementation of AES S-box in LUT-6 FPGAs

Advanced Encryption Standard (AES) is a symmetric cryptographic algorithm used for protecting data. Designing efficient hardware architecture for AES with small hardware resource usage is a challenge. AES uses different data transformations and the most expensive one, in terms of computational resources, is the SubBytes transformation which is carried out by a Look-Up-Table (LUT) named the S-box. In this paper, an efficient implementation of the S-box on LUTs-6 of an FPGA circuit of Virtex-5 is presented. This has reduced both occupied area and execution time, where the reading time of an S-Box is that of one slice.