• DocumentCode
    375361
  • Title

    Applying caching to two-level adaptive branch prediction

  • Author

    Egan, Colin ; Steven, Gordon B. ; Shim, Won ; Vintan, Lucian

  • Author_Institution
    Hertfordshire Univ., Hatfield, UK
  • fYear
    2001
  • fDate
    2001
  • Firstpage
    186
  • Lastpage
    193
  • Abstract
    During the 1990s Two-level Adaptive Branch Predictors were developed to meet the requirement for accurate branch prediction in high-performance superscale processors. However, while two-level adaptive predictors achieve very high prediction rates, they tend to be very costly. In particular, the size of the second level Pattern History Table (PHT) increases exponentially as a function of history register length. Furthermore, many of the prediction counters in a PHT are never used; predictions are frequently generated from non-initialised counters and several branches may update the same counter, resulting in interference between branch predictions. In this paper, we propose a Cached Correlated Two-Level Branch Predictor in which the PHT is replaced by a Prediction Cache. Unlike a PHT, the Prediction Cache saves only relevant branch prediction information. Furthermore, predictions are never based on uninitialised entries and interference between branches is eliminated. We simulate three versions of our Cached Correlated Branch Predictors. The first predictor is based on global branch history information while the second is based on local branch history information. The third predictor exploits the ability of cached predictors to combine both global and local history information in a single predictor. We demonstrate that our predictors deliver higher accuracy than conventional predictors at a significantly lower cost
  • Keywords
    cache storage; parallel architectures; program compilers; cached correlated branch predictors; caching; high-performance superscale processors; local history information; two-level adaptive branch prediction; Accuracy; Adaptive arrays; Costs; Counting circuits; History; Interference elimination; Pipelines; Predictive models; Registers; Silicon;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Digital Systems Design, 2001. Proceedings. Euromicro Symposium on
  • Conference_Location
    Warsaw
  • Print_ISBN
    0-7695-1239-9
  • Type

    conf

  • DOI
    10.1109/DSD.2001.952280
  • Filename
    952280