Exploiting multi-core SoC architecture for MU-MIMO schedulers

Upcoming standards are moving towards multi-antenna multiple-input multiple-output (MIMO) transmission techniques to harness the benefits of spatial degrees of freedom (DoF) in addition to the conventional time and frequency resources. Even though single user MIMO transmission improves the throughput noticeably, multiplexing different user data streams across the spatial dimension as in multi-user MIMO enhances the overall cell throughput significantly. However, this improved performance depends on the efficient selection of the users to be multiplexed over the spatial DoF. In this work, we compare the performance of different scheduling schemes in terms of achievable sum throughput and the overall complexity involved in the implementation for the real-time system requirements. The performances of the proposed schemes are evaluated on MATLAB for various MIMO configurations. The complexity analysis is carried out by implementing the scheduler algorithms on TI TCI6636K2H evaluation platform. We evaluate the complexity by sharing the load across eight TMS320C66x DSP core subsystem on the (system-on-chip) SoC.