MAD7F: A FPGA-based CMP Memory Architecture Simulation Framework

Increasing the number of processing cores on chip multiprocessors has become a mainstream strategy to boost their capabilities. At the same time, there is a need for tools to help design on-chip memory architectures supporting these newly added cores. Such tools are usually fully implemented in software which are unfortunately difficult to scale, partly because of the difficulty to compute concurrent timings efficiently. We present MAD7F, a framework that relies on delegating most of the memory architecture simulation aspects to hardware. In this framework, a host is in charge of providing memory access traces on-the-fly via PCIe to a simulator implemented on a FPGA that handles concurrent timings naturally. By doing so, no core architectures need to be implemented and memory architectures featuring high core counts can be simulated running virtually any kind of workloads, even with a modest simulation environment setup.