DocumentCode
3757199
Title
Yet Another Waiting Mechanism Based on Conflict Prediction for Hardware Transactional Memory
Author
Keisuke Mashita;Sho Miyake;Ryohei Yamada;Tomoaki Tsumura
Author_Institution
Nagoya Inst. of Technol., Nagoya, Japan
fYear
2015
Firstpage
400
Lastpage
403
Abstract
Transactional Memory (TM) has been proposed and studied for lock-free synchronization. On TMs, transactions are executed speculatively in parallel as long as they do not encounter any conflicts on shared variables. On general HTMs: hardware implementations of TM, transactions which have conflicted once each other will conflict repeatedly if they will be executed again in parallel, and the performance of HTM will be declined. To address this problem, in this paper, we propose a conflict prediction to avoid conflicts in advance based on historical data of conflicts. The result of the experiment shows that the execution time of HTM is reduced 63.5% in maximum, and 19.6% in average with 16 threads.
Keywords
"Hardware","Benchmark testing","Synchronization","System recovery","Electronic mail","Memory management"
Publisher
ieee
Conference_Titel
Computing and Networking (CANDAR), 2015 Third International Symposium on
Electronic_ISBN
2379-1896
Type
conf
DOI
10.1109/CANDAR.2015.57
Filename
7424746
Link To Document