Register Port Prediction for a Banked Register File

A large multi-port register file is an indispensable component to achieve higher computing performance, especially in recent processors. However, the number of its ports effects to circuit scale, access latency and power consumption significantly. Bank memory is one solution to implement a multi-port memory effectively. However, performance of the bank memory is lower than that of ideal multi-port memory. In order to reduce performance degradation caused by bank conflict, this paper proposes register write-back port prediction mechanism. This paper also implements the proposed prediction mechanism into a superscalar processor and estimates performance, access latency, circuit scale, and power consumption.