A 0.5-mA ultra-low-power low noise amplifier in 0.13 ?m CMOS

This paper presents an ultra-low-power design technique for CMOS low noise amplifiers. Parallel capacitance with input transistor Cgs is discussed for reducing gate induced noise and make it an effective way to implement low power LNA with small transistor size and moderate biasing condition. This technique is more effective for advanced process with high transition frequency. A low power LNA is implemented with 0.13μm CMOS, whose current is 0.5mA at 1.2V power supply. The noise figure is as low as 0.54dB while power gain is higher than 17dB.