Optimized hardware algorithm for integer cube root calculation and its efficient architecture

Scientific applications, digital signal processing, and multimedia usually need to compute a large number of arithmetic operations. One of them is cube root operation. It is one of the fundamental arithmetic operation which is not received much attention. Because of its calculation complexity, cube root is difficult to implement in Field Programmable Gate Array (FPGA). Hence in this paper, we propose an optimized hardware algorithm for integer cube root calculation and its efficient architecture. Integer cube root calculation is computed by using 3-digits of binary number and iterative calculation. An optimized hardware algorithm idea is reducing computational complexity in factor generator unit. For design evaluations, we use 32-bit integer cube root architecture and simulate it with several test vectors. Evaluation results show us that the design architecture is valid. The design latency is defined by (N/3)+2, with N is bit-width of the design input. Hence, 32-bit design will be executed only in ((32+1)/3)+2 = 13 clock cycles. The design also has been synthesized for several FPGA implementation with promising results in area consumption and speed.