A 100-MHz 51.2-Gb/s packet lookup engine LSI based on missmatch detection circuit combined with linked-list hash table

Developing an extremely efficient packet inspection algorithm for lookup engines is important to realize a high throughput and a lower energy dissipation. Previously, we proposed a mismatch detection circuit that detects mismatches with a minimal amount of memory accesses. In the present paper, we propose a new lookup engine based on the combination of a mismatch detection circuit and a linked-list hash table. An experimental chip was fabricated in 40-nm 8-metal CMOS process technology. The chip operates at a frequency of 100 MHz under a power supply voltage of VDD=1.1 V. The throughput of 100 Mpacket/s (=51.2 Gb/s) is obtained at a frequency of 100 MHz, which is 3 times greater when compared to the 33 M Mpacket/s of a lookup engine without a mismatch detection circuit. The measured energy dissipation is 0.808 nJ/Search. The proposed lookup engine improves the packet inspection throughput and reduces energy dissipation.