Design of high speed Vedic multiplier using multiplexer based adder

Real time applications such as controlling environmental conditions demand quick response of the processor for processing the acquired signals. Multiplier is an important feature of signal processing. Vedic Mathematics provides principles of high speed multiplication. Motivated by this, a high speed Vedic multiplier using multiplexer based adder is proposed in this paper. Proposed design is simulated using ModelSim and synthesized using Xilinx ISE 14.7. When compared with existing Vedic multipliers, proposed design shows a significant improvement in speed.