A reconfigurable 2-D IDCT architecture for HEVC encoder/decoder

Recently, HEVC standard have been proposed as a solution for transmitting high quality videos with half bit rate compared to the previous H.264 standard. One of the main properties of the new standard is the variety of the transform unit sizes. In this paper, we propose a new reconfigurable pipelined architecture for Inverse Discrete Cosine transform, which is used in both the HEVC encoder and decoder. Our circuit supports all the transform block sizes with reusability and reconfigurability of the different circuit parts. Our proposed architecture implemented on TSMC 65nm, runs at clock frequency of 500 MHz, and achieves throughput of 1990 Mpixel/sec that is more than the best architecture in the literature, to the best of our knowledge, by about 42%. The proposed architecture can process UHD video resolutions up to 8K with 60 fps.