Yield estimation of CNFET-based circuits with imperfections

One of the major challenges faced by CNFET technology is unwanted growth of metallic tubes that adversely affect the performance, power, and yield of circuits designed with CNFETs. Selective Chemical Etching (SCE) and VLSI-Compatible Metallic-Carbon-Nanotube Removal (VMR) techniques have been proposed to remove the unwanted metallic tubes. Unfortunately, both of these techniques also remove a large fraction of semiconducting tubes. Tube removal can result in degradation of circuit performance and non-functioning open-circuit logic gates. We have developed analytical models to quickly estimate the functional yield of CNFET-based circuits, in the presence of metallic tubes, and after their removal. The absolute difference in functional yield magnitudes between Monte Carlo simulations and our analytical models differ between 0.4% and 2.6% for an inverter, and between 0.2% and 3.4% for NAND/NOR gates.