Hardware IP Protection through Gate-Level Obfuscation

Hardware Intellectual Property (IP) cores have emerged as an integral part of modern System-on-Chip (SoC) designs. However, recent trends of reverse engineering pose major threat to IP-based SOC design flow. The paper proposes a novel approach for hardware IP protection using gate-level obfuscation, which could make design less intelligible in order to neutralize or weaken the effect of reverse engineering. The basic idea is to hide the original logic function by using Physical Unclonable Function (PUF), multiplexer and configurable logic, so that it is difficult for reverse engineering attackers to get complete information of circuit net list. The design methodology could be applied in combinational logic and sequential logic. Simulation results on several IP cores show that we can achieve high levels of security through a well-formulated obfuscation scheme at less than 10% area overhead under delay constraint.