HW/SW Partitioning Algorithm Targeting MPSOC with Dynamic Partial Reconfigurable Fabric

With the development of technology, the architecture of embedded systems is no longer homogeneous. Some of them integrate multi-core processors, and some FPGA-based embedded systems support fabrics with dynamic partial reconfiguration (DPR) capability. As a result, traditional hardware/software (HW/SW) partitioning algorithms are no longer suitable. We propose a new MILP (Mixed Integer Linear Programming) formulation to deal with HW/SW partitioning targeting MPSOC (Multi-core Processor System on Chip) with a DPR fabric. Moreover, to help explore the solution space of large scale problems, we propose a method which integrates a heuristic method and an MILP formulation. The experiments show that our approach converges quickly so that results with good quality can be achieved in a reasonable amount of time.