Title :
An ultra fast on-chip bist of transmitter I/Q mismatch and non-linearity using envelope detector
Author :
V. Jayanthi;V. Niveatha Saro
Author_Institution :
Department of ECE, J.J. College of Engg. & Tech, Trichy
Abstract :
A built-in self-test (BIST) is a mechanism that permits a machine to test itself. The main purpose of BIST is to reduce the complexity, and thereby decrease the cost and reduce reliance upon external test equipment. Existing on-chip resources, such as power or envelope detectors or small additional circuitry, can be used for BiST purposes. However, due to limited bandwidth, measurement of complex specifications, such as in-phase and quadrature (IQ) imbalance, and third-order inter modulation intercept point (IIP3) is challenging. Since IQ imbalances are most amenable for digital compensation, their characterization and monitoring are desirable. In this paper, we propose a multistep BiST technique for transmitter IQ imbalance and nonlinearity using a self mixing envelope detector. We derive analytical expressions for the output signal in linear and nonlinear modes. In the next step, using a higher power test signal, the nonlinear behavior of the transmitter is excited and the IIP3 of the transmitter is computed based on the analytical expressions. One of the glaring advantages of this method is that, the impairments are extracted from analyzing the response at base band frequency and thereby eliminating the need of high frequency ATE(Automated Test Equipment).
Keywords :
"Transmitters","Radio frequency","Mathematical model","Envelope detectors","System-on-chip","Built-in self-test"
Conference_Titel :
Green Engineering and Technologies (IC-GET), 2015 Online International Conference on
DOI :
10.1109/GET.2015.7453779