DocumentCode :
3768177
Title :
A reconfigurable coprocessor units with redundant radix-4 arithmetic
Author :
S Shinde Abhijeet;S Jambhale Vidyadhar;P Deore Gaurav;S Sivanantham;K Sivasankaran
Author_Institution :
School of Electronics Engineering, VIT University, Vellore - 632014, India
fYear :
2015
Firstpage :
1
Lastpage :
4
Abstract :
Performance in many very-large-scale-integrated (VLSI) systems such as digital signal processing (DSP) chips, is predominantly determined by the speed of arithmetic modules like adders and multipliers. In recent times, designing coprocessors for fast arithmetic operation has become an important field of research. This paper implements a Reconfigurable Coprocessor for Redundant Radix-4 Arithmetic. In this coprocessor, we have implemented addition, subtraction, NAND, EXOR. In this paper, we have developed a complete set of Verilog modules, synthesized and implemented by targeting Altera Cyclone II FPGA.
Keywords :
"Coprocessors","Very large scale integration","Field programmable gate arrays","Algorithm design and analysis","Signal processing algorithms","Computers","Adders"
Publisher :
ieee
Conference_Titel :
Green Engineering and Technologies (IC-GET), 2015 Online International Conference on
Type :
conf
DOI :
10.1109/GET.2015.7453804
Filename :
7453804
Link To Document :
بازگشت