DocumentCode :
3769961
Title :
Analysis of Graphene Nanoribbon (GNR) interconnects with multi-gate device technology for VLSI applications
Author :
Vangmayee Sharda;R. P. Agarwal
Author_Institution :
Amity University, Uttar Pradesh
fYear :
2015
Firstpage :
1
Lastpage :
6
Abstract :
Challenges from interconnects in the deep submicron VLSI domain are now a days addressed through the new inventions. These inventions include device as well as interconnect technology domain. Materials based on Graphene such as Carbon Nanotubes and Graphene Nanoribbons are the two capable candidates to replace the traditional Cu in deep-nanometer VLSI interconnect. Multilayer graphene nanoribbon is making headway as an imminent nominee for deep-submicron regime interconnects with help of its properties like superior conductivity and high current carrying capabilities. FinFETs, the device with several gates are the most encouraging structure at device level in nano VLSI technology. In this research paper we have compared the performance of DIL system of conventional CMOS and MLGNR interconnects with DIL system of new device technology FinFET with MLGNR interconnect.
Keywords :
"Delays","FinFETs","Integrated circuit interconnections","Graphene","Crosstalk","Electronics packaging","Performance evaluation"
Publisher :
ieee
Conference_Titel :
Electrical Computer and Electronics (UPCON), 2015 IEEE UP Section Conference on
Type :
conf
DOI :
10.1109/UPCON.2015.7456742
Filename :
7456742
Link To Document :
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