DocumentCode
377121
Title
A low-voltage fully differential CMOS high-speed sample-and-hold circuit
Author
Lee, Tsung-Sum ; Hsiao, Kai-Ren
Author_Institution
Dept. of Electron. Eng., Nat. Yunlin Univ. of Sci. & Technol., Taiwan
Volume
1
fYear
2001
fDate
2001
Firstpage
235
Abstract
A new technique for realizing a low-voltage fully differential CMOS high-speed sample-and-hold (S/H) circuit is presented. The design consideration of the building blocks is described in detailed. Simulation results are given to demonstrate the potential advantage of the new technique
Keywords
CMOS analogue integrated circuits; high-speed integrated circuits; low-power electronics; sample and hold circuits; CMOS; building blocks; design consideration; fully differential circuit; high-speed circuit; low-voltage circuit; sample-and-hold circuit; Capacitance; Capacitors; Circuit noise; Circuit simulation; Clocks; Differential amplifiers; Noise reduction; Samarium; Sampling methods; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 2001. MWSCAS 2001. Proceedings of the 44th IEEE 2001 Midwest Symposium on
Conference_Location
Dayton, OH
Print_ISBN
0-7803-7150-X
Type
conf
DOI
10.1109/MWSCAS.2001.986157
Filename
986157
Link To Document