DocumentCode
377141
Title
A 1.6-GHz 16x16b asynchronous pipelined multiplier
Author
Sin, Tze-Yee ; Wong, Eddie M C ; Jong, Ivan C C
Author_Institution
Sch. of Electr. & Electron. Eng., Nanyang Technol. Univ., Singapore
Volume
1
fYear
2001
fDate
2001
Firstpage
336
Abstract
This paper presents a 16×16 b fully pipelined multiplier for fine-grain DSP applications. A novel asynchronous handshake protocol is employed to replace the conventional global clock. Based on 0.25 μm CMOS technology, HSPICE simulation results indicate that an average data throughput of 1.6 GHz can be achieved at 1.8 V operation
Keywords
CMOS logic circuits; SPICE; asynchronous circuits; digital signal processing chips; multiplying circuits; pipeline arithmetic; 0.25 micron; 1.6 GHz; 1.8 V; 16 bit; CMOS technology; HSPICE simulation; asynchronous handshake protocol; fine-grain DSP; fully-pipelined multiplier; CMOS technology; Circuits; Clocks; Concurrent computing; Detectors; Digital signal processing; Equations; Pipelines; Protocols; Throughput;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 2001. MWSCAS 2001. Proceedings of the 44th IEEE 2001 Midwest Symposium on
Conference_Location
Dayton, OH
Print_ISBN
0-7803-7150-X
Type
conf
DOI
10.1109/MWSCAS.2001.986181
Filename
986181
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