A programmable Reed-Solomon codec processor

Author

Zheng Xiong Chen ; Shen, Nan-Ying ; Chen, Oscal T C ; Hsu, Yuh-Feng ; Tsen, Yuh-Jou ; Perng, Daniel Y.

Author_Institution

Dept. of Electr. Eng., Nat. Chung Cheng Univ, Taiwan

Volume

1

fYear

2001

fDate

2001

Firstpage

359

Abstract

We propose a Reed-Solomon (RS) codec processor that can have programmable error-correction number of 1 to 10, and codeword length of 8 to 255. The proposed RS codec processor includes an encoder and a decoder. Especially in the decoder, we use a modified Fermat algorithm to reduce the complexity of the division. By using the cell library of the TSMC 0.35 μm CMOS technology, the proposed RS codec processor was implemented with a die size of 5.1×5.0 mm². It can operate at 50 MHz to yield the throughput rate of 50 Msamples per second where each sample is 8 bits

Keywords

CMOS digital integrated circuits; Reed-Solomon codes; VLSI; codecs; digital signal processing chips; error correction codes; programmable circuits; 0.35 micron; 50 MHz; RS decoder; RS encoder; Reed-Solomon codec processor; TSMC CMOS technology; VLSI architecture; division complexity reduction; modified Fermat algorithm; programmable codec processor; programmable error-correction number; CMOS process; CMOS technology; Codecs; Decoding; Error correction; Error correction codes; Libraries; Reed-Solomon codes; Signal processing; Throughput;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2001. MWSCAS 2001. Proceedings of the 44th IEEE 2001 Midwest Symposium on

Conference_Location

Dayton, OH

Print_ISBN

0-7803-7150-X

Type

conf

DOI

10.1109/MWSCAS.2001.986187

Filename

986187