A 1 GHz 1.8 V monolithic CMOS PLL with improved locking

Author

Zhou, Jian ; Chen, Huiting

Author_Institution

Texas Instrum. Inc., Dallas, TX, USA

Volume

1

fYear

2001

fDate

2001

Firstpage

458

Abstract

A 1 GHz 1.8 V monolithic CMOS phase-locked loop (PLL) circuit for high-speed serial bus applications is presented. The monolithic PLL consists of a dead-less phase frequency detector, a charge pump, a bias generator circuit with an auxiliary bias generator to secure locking, a voltage-controlled oscillator and a differential to single-ended converter with duty cycle correction. A startup circuit is added to prevent the PLL from false locking and to expedite the locking. The PLL has been fabricated in a 0.18 μm CMOS technology, occupying an active area of 0.02 mm². The PLL can operate from 100 MHz up to 1.2 GHz and consumes less than 10 mW from a 1.8 V supply

Keywords

CMOS analogue integrated circuits; data communication equipment; high-speed integrated circuits; jitter; low-power electronics; phase locked loops; 0.18 micron; 1 GHz; 1.8 V; 10 mW; 100 MHz to 1.2 GHz; auxiliary bias generator; bias generator circuit; charge pump; damping factor; dead-less phase frequency detector; differential to single-ended converter; duty cycle correction; high-speed data communication; high-speed serial bus applications; improved locking; locking time; monolithic CMOS PLL; peak-to-peak jitter; power consumption; startup circuit; voltage-controlled oscillator; CMOS technology; Charge pumps; Circuits; Clocks; Delay; Jitter; Phase frequency detector; Phase locked loops; Signal generators; Voltage-controlled oscillators;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2001. MWSCAS 2001. Proceedings of the 44th IEEE 2001 Midwest Symposium on

Conference_Location

Dayton, OH

Print_ISBN

0-7803-7150-X

Type

conf

DOI

10.1109/MWSCAS.2001.986211

Filename

986211