DocumentCode
377414
Title
Switching activity in parallel multipliers
Author
De Angel, Edwin ; Swartzlander, Earl E., Jr.
Author_Institution
Crystal Semicond. Product Div., Cirrus Logic Corp., Austin, TX, USA
Volume
1
fYear
2001
fDate
4-7 Nov. 2001
Firstpage
857
Abstract
This paper presents a study in the switching activity of parallel multipliers. Modified-Booth multipliers are used to compare carry save implementations with different optimization techniques and multipliers using redundant binary representations. Signal correlation and random sets of data used for simulation show the impact on switching activity and how architectures are suited for different applications.
Keywords
adders; circuit optimisation; correlation theory; parallel architectures; redundant number systems; switching circuits; architectures; carry save implementations; modified-Booth multipliers; optimization; parallel multipliers; random sets; redundant binary representations; signal correlation; simulation; switching activity; Algorithm design and analysis; Arithmetic; CMOS logic circuits; Clocks; Delay; Digital signal processing; Encoding; Feeds; Power dissipation; Signal generators;
fLanguage
English
Publisher
ieee
Conference_Titel
Signals, Systems and Computers, 2001. Conference Record of the Thirty-Fifth Asilomar Conference on
Conference_Location
Pacific Grove, CA, USA
ISSN
1058-6393
Print_ISBN
0-7803-7147-X
Type
conf
DOI
10.1109/ACSSC.2001.987045
Filename
987045
Link To Document