DocumentCode
3775131
Title
NAND technology
Author
Krishna Parat
Author_Institution
Intel Corporation, United States
fYear
2013
Firstpage
1
Lastpage
18
Abstract
NAND Flash has a simple array structure which has been highly amenable to scaling; NAND Flash leads the industry in scaling; Lithography induced scaling limits were overcome using advanced pitch reduction techniques; Interference issues were contained through incorporation of air-gap at critical locations; Wrap cell limits were overcome with planar FG cell using High-K dielectric / Metal gate; 2D scaling can continue into the mid to low ~10nm; Scaling beyond can come from transitioning to 3D.
Keywords
"Logic gates","Nonvolatile memory","Flash memories","Programming","NAND memory","Grounding"
Publisher
ieee
Conference_Titel
Hot Chips 25 Symposium (HCS), 2013 IEEE
Type
conf
DOI
10.1109/HOTCHIPS.2013.7478292
Filename
7478292
Link To Document