Optimization of an Arithmetic Logic Unit using generic floating point algorithm for 12-Bit Architecture

A proposed high speed generic floating point algorithm for 12-Bit Architecture is consist of adder, subtractor, multiplier, divisor, square root, and cube root modules. A novel algorithm was proposed for each modules using VHDL to optimize the speed and area as well as to attain the highest maximum operating frequency. A top down approach was applied for the modules and these were further subdivided into sub-modules for the two inputs to be combined. The novel algorithm was written in VHDL code, simulated in Xilinx 9.2i and 13.1 version and implemented in Xilinx FPGA Virtex boards. The results were analyzed and compared with different algorithms. As the FPGAs´ (Field Programmable Gate Array) popularity increases rapidly, they are becoming more suitable in many applications that require dense computations and high frequency. The improvement in the performance of electronic systems can be traced to developments in integrated circuits which form the fundamental building blocks of modern electronics technology. As with the modern technology fast-approaching, the development of integrated circuits can also be attributed with the help of hardware description language (HDL) such as VHDL and Verilog. The need to improve the face of the ICs through the use HDL also defines the speed and area of the whole circuitry. The basis for conceptualizing the design, development, and evaluation of a generic algorithm is to provide a direct impact of improving the existing modules that was implemented on many design applications in DSP. Prior, to the development of the VHDL modules, other studies involving ALU similar to the paper were considered to determine the parameters to be observed. The enhancement of the existing VHDL modules in the other papers are implemented for the ALU and this includes the development of the new modules such as the square and cube root.