DocumentCode
3777792
Title
Simplification of the scheme of the self-tested detector (m, w)-code
Author
N. Butorina
Author_Institution
Tomsk State University, Tomsk, Russia
fYear
2015
Firstpage
1
Lastpage
4
Abstract
The article is devoted to the improvements of a self-tested checker (m, n) - codes, constructed within FPGA technology.
Keywords
"Circuit faults","Built-in self-test","Field programmable gate arrays","Single event upsets","Cognition","Computers"
Publisher
ieee
Conference_Titel
East-West Design & Test Symposium (EWDTS), 2015 IEEE
Type
conf
DOI
10.1109/EWDTS.2015.7493137
Filename
7493137
Link To Document