A power based memory BIST grouping methodology

For System-on-Chips (SoCs) one of the most critical design constraints is power consumption. This paper presents memory built-in self-test (BIST) grouping methodology which takes into account the given peak power, power domains based on Unified Power Format (UPF) and optimal test time. The mentioned grouping criteria enable to perform power-aware memory BIST design at early stages of SoC design. To apply this methodology, there is a need for a method to estimate the power consumption from a design description of the circuit at high level of abstraction. We propose a fast power estimation methodology for register-transfer level (RTL) compilers which is based on linear and polynomial approximation. The obtained approximate functions are embedded in a script developed for automated estimation of power consumption. Memory BIST grouping methodology is based on and uses the data of power consumption estimation script as input information.