Defect-aware methodology for low-power scan-based VLSI testing

Modern IC design and VLSI manufacturing techniques continued to race over the next decade following the rule of twenty. The transistor count on a single chip is escalating exponentially with complex embedded & DSP cores, as a trend by virtue of Moore´s formula of number of transistors doubling every 18 months on a chip[1-3]. Consequently, Problem of VLSI testing is growing by few manifolds, especially for next-generation designs lower than 22nm and as a result, Power-Aware test is increasingly becoming a major manufacturing test consideration due to the problems of test implications that arise from the usage of low-power designs. Heuristics are surveyed to address various power-aware test problems and challenges and proposed a unified low-power and defect-aware x-fillling novelty to reduce the test power in the scan-based test. The proposed method reduces test power significantly during both test and functional operation. Also the proposed pattern based ATPG technique furnishing experimental results and interpolated graphs brings a good assessment of switching activity reduction for both academia and industry. It gives good industrial performance bounds to fill the gaps between DFT and ATPG flows and helps the switching acclivities and pattern count while maintaining the same coverage, indeed reducing test-power to 65-80%.