Design of a Network on Chip router based on turn model

The systems of interconnection play a major role in the performance expected by System on chip (SoC). With the evolution of technology, conventional shared-bus based interconnections are no longer the ideal solution for the future SoC. Therefore Network on chip (NoC) is emerging as a perfect solution to enhance the communication structures for future SoC. Compared with the conventional interconnection schemes, NoC ensures high performance and scalability. To overcome those limitations, in this paper we presents the design of a NoC router based on turn model. A Turn Model routing algorithm is used to avoid deadlock conflicts. Also the router integrates a dynamic arbiter to increase the Quality of Service of network. To evaluate performance of our design, we compared it with famous router in terms of area, power and clock frequency.