Relationship between gate bias and hot-carrier induced instabilities in p-channel MOSFETs

The stability of short p-channel MOSFETs with respect to hot-carrier phenomena is a growing area of concern for VLSI [1-5], It is generally accepted that Instabilities in p-channel transistors are maximized at stress bias conditions that cause the peak gate current to flow [1-3] rather than the peak substrate current as in the case of n-channel devices. However, contrary observations have been reported [4,5]. This paper presents the results of a detailed study of the effects of stress bias conditions on shifts in several important device parameters. The results indicate that for certain parameters, maxima in the magnitude of observed shifts can correspond to peaks in both gate and substrate currents. This observation is important for future reliability studies of short p-channel MOSFETs.