Title :
Optimal design on asynchronous system with gate-level pipelining
Author :
Masato Tamura;Atsushi Ito;Makoto Ikeda
Author_Institution :
Department of Electrical Engineering and Information System, The University of Tokyo, 7-3-1-107 Hongo, Bunkyo-ku, Tokyo, 113-8656, Japan
Abstract :
Automatic optimal design of asynchronous system based on gate-level handshake pipelined control is proposed. Gate-level alignment, fan-out and loop optimization are important to maintain throughput of the system. With netlist generated from RTL by a commercially available logic synthesize tool, our method optimizes insertion of buffers to optimally align among gates. Benchmark results show the proposed method realizes about 1.3× higher throughput than synchronous circuit in 65nm process, with area increase of 15×.
Keywords :
"Logic gates","Throughput","Pipeline processing","Timing","Latches","Benchmark testing","Rails"
Conference_Titel :
ASIC (ASICON), 2015 IEEE 11th International Conference on
Print_ISBN :
978-1-4799-8483-1
Electronic_ISBN :
2162-755X
DOI :
10.1109/ASICON.2015.7516904
