DocumentCode :
3781242
Title :
A full layer parallel QC-LDPC decoder for WiMAX and Wi-Fi
Author :
Wenchao Zhang;Song Chen;Xuefei Bai;Dajiang Zhou
Author_Institution :
Dept. of Electronic Sci. & Tech., University of Science and Technology of China, Hefei 230027, China
fYear :
2015
Firstpage :
1
Lastpage :
4
Abstract :
This paper presents a full layer parallel quasi-cyclic low density parity check (QC-LDPC) code decoder for IEEE 802.16e (WiMAX) and IEEE 802.11n (Wi-Fi). By adopting three techniques including reusable fully parallel check node unit (CNU) structure, path rerouting network (PRN) and reusable permutation network (PN), the proposed decoder gets Gbps level throughput and could support two standards and most code modes of them with low hardware cost. By using turbo-decoding message-passing normalized min-sum (TDMP-NMS) decoding strategy, the bit error rate (BER) of the proposed decoder is decreasing fast to 10-5 at 2.2 dB. It only takes 30~40/30~60 clock cycles in each decoding iteration for WiMAX/Wi-Fi. Using SMIC 40nm low leakage HS RVT CMOS process and 7-bit quantization, the proposed decoder attains 789~2227/470~1879 Mbps for WiMAX/Wi-Fi at 290 MHz, 10 iterations, and only occupies 2.26 mm2 area.
Keywords :
"Decoding","WiMAX","IEEE 802.11 Standard","Clocks","Phase change materials","Computer architecture","Parity check codes"
Publisher :
ieee
Conference_Titel :
ASIC (ASICON), 2015 IEEE 11th International Conference on
Print_ISBN :
978-1-4799-8483-1
Electronic_ISBN :
2162-755X
Type :
conf
DOI :
10.1109/ASICON.2015.7517004
Filename :
7517004
Link To Document :
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