An 8-bit 4fs-step digitally controlled delay element with two cascaded delay units

To meet the rapidly growing demands of ADC speed and resolution, time-interleaved ADC (TI-ADC) is one of the hot topics. However, there are intrinsic problems such as clock skew and gain error between channels. As a key element of TI-ADC to overcome these problems, a high resolution and linearity Digitally Controlled Delay Element (DCDE) is designed. The DCDE consists of two-level cascaded delay units, coarse tuning and fine tuning, controlled by 32 bits thermal code and 8 bits binary code respectively, with about 4fs step size and 30ps full scale. The circuit is simulated and realized in TSMC 65nm CMOS process, with area of 790 × 650μm² and low power dissipation, which varies with input frequency and consumes 2.3mW at 8GHz clock rate.